1. Field of the Invention
The present invention relates to a level converter circuit, and more particularly, to a level converter circuit for a flash memory.
2. Description of the Background Art
In a flash memory, a voltage of various levels must be applied to a memory cell. In the case of a DINOR type flash memory, for example, various voltages of a level indicated in the following Table 1 must be applied to a bit line, a word line, and a source line in various operation modes. In Table 1, the voltage at the left side of the slash sign is supplied at a select state, and the voltage at the right side of the slash sign is applied at a de-select state.
TABLE 1 ______________________________________ Bit line Word line Source line ______________________________________ Program 6V/0V -9V/0V Floating Erase Floating 10V/0V 9V Read 1V 3.3V/0V 0V ______________________________________
Referring to Table 1, a voltage of 6V and a voltage of -9V are applied to a bit line and a word line, respectively, and a source line is set to a floating state for a selected memory cell in a program operation mode. For a de-selected memory cell, a voltage of 0V is applied to the bit line and the word line, and the source line is set to a floating state.
In an erase operation mode, the bit line is set to a floating state, and a voltage of 10V and a voltage of -9V are applied to the word line and the source line, respectively, for a selected memory cell. For a de-selected memory cell, the bit line is set to a floating state, and a voltage of 0V and a voltage of -9V are applied to the word line and the source line, respectively.
In a read operation mode, a voltage of 1V, a voltage of 3.3V, and a voltage of 0V are applied to the bit line, the word line, and the source line, respectively, for a selected memory cell. For a de-selected memory cell, a voltage of 1V is applied to the bit line, and a voltage of 0V is applied to the word line and the source line.
It is appreciated that a level converter circuit for supplying a voltage of various levels is required. An example of a conventional level converter circuit is shown in FIG. 16.
Referring to FIG. 16, a level converter circuit 501 includes cross-coupled P channel MOS transistors 507 and 508, and N channel MOS transistors 509 and 510 turned on/off in a complementary manner in response to a voltage switching signal Vin.
When voltage switching signal Vin of an H (logical high) level is applied, N channel MOS transistor 510 is turned on. Since this voltage switching signal Vin is applied to the gate of N channel MOS transistor 509 via an inverter 511, N channel MOS transistor 509 is turned off. As a result, the voltage of node 506 is pulled down to a level of ground voltage (0V) GND, whereby P channel MOS transistor 507 is turned on. Therefore, voltage Vpp of a voltage input terminal 102 is provided as an output voltage Vout via P channel MOS transistor 507.
When voltage switching signal Vin of an L (logical low) level is applied, N channel MOS transistor 510 is turned off and N channel MOS transistor 509 is turned on. Therefore, the voltage of node 505 is pulled down to the level of ground voltage GND, whereby P channel MOS transistor 508 is turned on. Here, voltage VPP is applied to the gate of P channel MOS transistor 507 via P channel MOS transistor 508, whereby P channel MOS transistor 507 is turned off. Therefore, ground voltage GND is provided as output voltage Vout via N channel MOS transistor 509.
Thus, level converter circuit 501 provides an output voltage Vout of a VPP level in response to voltage switching signal Vin of an H level, or output voltage Vout of a ground level in response to voltage switching signal Vin of an L level. A circuit that converts the voltage level by switching cross-coupled transistors 507 and 508 as shown in FIG. 16 is referred to as a cascade voltage switch logic (CVSL) circuit.
By using this CVSL circuit, a level converter circuit that generates only a positive voltage with an amplitude between the level of VPP and ground can be implemented. However, this level converter circuit cannot selectively generate positive and negative voltages as shown in Table 1.